In the meantime, semiconductor memories have recently been commercialized which include pulse generators adapted to produce internal circuit control signals through detection of the transitions, viz., the rise and fall of address input signals, for achieving reduction in the power dissipation of the memory devices. A memory device of this nature necessitates the provision of as many pulse generators as there are address input lines used for the memory device. For example, a memory device having the storage capacity of 64 kilowords must use sixteen pulse generators for the 16 bits per address. If each of such pulse generators is implemented using the C-MOS circuit hereinbefore described with reference to FIG. 2, a total of 384 circuit components must be used in view of the twenty two transistors and two capacitors which form each of the pulse generators. Where the pulse generators are implemented as on-chip circuits in the memory device, they will occupy a disproportionately large space on the chip and will thus make it extremely difficult to realize a mass memory with a desired storage capacity. This is a problem encountered in not only semiconductor memories but also in other types of semiconductor integrated circuits which use pulse generators responsive to the transitions of input signals.
Another problem in prior-art pulse generator circuits of the nature described with reference to FIGS. 1 and 2 is the requirement for the provision of two similar delay circuits 16 and 18 each including the capacitor 30 for the adjustment of the pulsewidth T (FIGS. 3A and 3B) of the pulses to be produced by the pulse generator circuit. This is objectionable not only from the view point of circuit configuration but because of the fact that the two capacitors 30 provided in the pulse generator circuit must be calibrated to have precisely equal time constants to provide a fixed pulsewidth T. Difficulties are however encountered in correctly calibrating the time constants of the two capacitors 30 and accordingly in providing a fixed pulsewidth.
It is therefore an important object of the present invention to provide an improved pulse generator circuit which is composed of a reduced number of circuit components and which will thus permit the use of a desired number of such circuits on a semiconductor device such as, typically, a semiconductor memory device.
It is another important object of the present invention to provide an improved pulse generator circuit which is capable of generating pulses with a correctly fixed pulsewidth.